Home Electrical Engineering Forum General Discussion Controller Area Network (CAN) bit stuffing

This topic contains 2 replies, has 0 voices, and was last updated by  gomathi.c 6 years, 5 months ago.

Viewing 3 posts - 1 through 3 (of 3 total)
  • Author
    Posts
  • #10882

    gomathi.c
    Member

    I was going through an article on CAN bus in Wikipedia & was stuck at the point where bit stuffing is explained. CAN is an asynchronous bus. They implement NRZ (Non-Return-To-Zero) encoding. To enable the receiver to correctly read the messages, continuous resynchronization is required.

     

    Generally, in NRZ, a problem arises when there is a long sequence of 0s or 1s and the voltage level is maintained at the same value for a long time. This creates a problem on the receiving end because now, the clock synchronization is lost due to lack of any transitions and hence, it is difficult to determine the exact number of 0s or 1s in this sequence.

     

    As per, http://www.softing.com/home/en/industrial-automation/products/can-bus/more-can-bus/bit-encoding/bit-stuffing-rule.php 

    One characteristic of Non-Return-to-Zero code is that the signal provides no edges that can be used for resynchronization if transmitting a large number of consecutive bits with the same polarity. Therefore bit-stuffing is used to ensure synchronization of all bus nodes.

    This means that during the transmission of a message, a maximum of five consecutive bits may have the same polarity. Then a bit is stuffed.

     

    What I don’t understand is, why in NRZ, a consecutive 0’s & 1’s don’t provide edge? I assume edge means a transition. Am I right? Kindly explain me. Thanks in advance.

    #13122

    Anonymous

    I tried to answer exactly, but when I was reading about NRZ and I was thinking about it then I realized that I don’t understand all of aspects.
    In my practice when I work with CAN and uses dedicated physical layer drivers that kinds of problems was resolved by hardware.

    #13034

    Anonymous

    CAN bus makes use of asynchronous signaling with NRZ codification and, therefore, sample operation in receivers is needed. So, in order that a CAN controller of a node, that is a synchronous digital system with frequency clock generated by an oscillator, could sample the received asynchronous signal with fiability and accuracy, it must use a higher sample frequency to the signal going through the bus.

    Whatsmore, real electrical signals in a CAN bus suffer from their own influences from distortion by physical characteristics, propagation delays, controller delays itself, EMI’s, and each member of a CAN network has its own clock, that normally is a quars clock with certain tolerance. So, a sample process and resynchronization are required in order to avoid clashing due to that factors.

    CAN spec defines:

    – Nominal bit frequency, that is the number of bits transmitted per second, with lack of resynchronization, realised by an ideal transmitter. Opposite value is Nominal bit time, Nbt.

    – As already told, CAN controller must use a clock frequency that is multiple of nominal bit frequency, got as oscillator frequency quocient. Minimum time quantum, Mtq, is defined the same as oscillator frequency (maybe same or maybe half frequency). Basic time quantum, Tq, whose opposite is controller basic frequency, is proportional to Mtq by means of a Baud rate prescaler, Brp, normally able to configuration. So, Tq=Brq·Mtq.

    Bit is sampled in a point into bit time. Communication speed in the controller settings, for a given oscillator frequency, is defined by Brp, and number of Tq per bit. This last value, Tq, is also obtained from an adding of partial values, also allowed to configuration that have some relation to bit synchornization.

    CAN fixes two sampling synchronization methods with frame sequence bits when talking about receiver nodes: Hard synchronization and Soft synchronization

    So, going back to the question, bit stream in a CAN message is coded according to the Non-Return-to-Zero (NRZ) method. This means that during the total bit time the generated bit level is either “dominant” or “recessive”.

    Bit stuffing is provided for Error Handling when Transfer Layer instead of Physical Layer.

Viewing 3 posts - 1 through 3 (of 3 total)

You must be logged or registered in to reply to this topic.

Electrical engineering Community, license Creative Commons License